_USB1Interrupt:
;HID_Read_Write.c,31 :: 		void USB1Interrupt() iv IVT_USB_1 ilevel 7 ics ICS_SRS{
RDPGPR	SP, SP
ADDIU	SP, SP, -12
MFC0	R30, 12, 2
SW	R30, 8(SP)
MFC0	R30, 14, 0
SW	R30, 4(SP)
MFC0	R30, 12, 0
SW	R30, 0(SP)
INS	R30, R0, 1, 15
ORI	R30, R0, 7168
MTC0	R30, 12, 0
ADDIU	SP, SP, -4
SW	RA, 0(SP)
;HID_Read_Write.c,32 :: 		USB_Interrupt_Proc();
JAL	_USB_Interrupt_Proc+0
NOP	
;HID_Read_Write.c,33 :: 		}
L_end_USB1Interrupt:
LW	RA, 0(SP)
ADDIU	SP, SP, 4
DI	
EHB	
LW	R30, 8(SP)
MTC0	R30, 12, 2
LW	R30, 4(SP)
MTC0	R30, 14, 0
LW	R30, 0(SP)
MTC0	R30, 12, 0
ADDIU	SP, SP, 12
WRPGPR	SP, SP
ERET	
; end of _USB1Interrupt
_main:
;HID_Read_Write.c,35 :: 		void main(void){
ADDIU	SP, SP, -4
;HID_Read_Write.c,36 :: 		int Count = 0;
MOVZ	R30, R0, R0
SH	R30, 0(SP)
;HID_Read_Write.c,37 :: 		TRISB.RB0 = 0; PORTB.RB0 = 0;
ORI	R2, R0, 1
SW	R2, Offset(TRISB+4)(GP)
SW	R2, Offset(PORTB+4)(GP)
;HID_Read_Write.c,38 :: 		AD1PCFG = 0xFFFF;                        // Configure AN pins as digital I/O
ORI	R2, R0, 65535
SW	R2, Offset(AD1PCFG+0)(GP)
;HID_Read_Write.c,40 :: 		USBIE_bit = 0;
LUI	R2, BitMask(USBIE_bit+0)
ORI	R2, R2, BitMask(USBIE_bit+0)
_SX	8, Offset(USBIE_bit+4), 4
;HID_Read_Write.c,41 :: 		IPC11bits.USBIP = 7;
ORI	R2, R0, 7168
SH	R2, Offset(IPC11bits+8)(GP)
;HID_Read_Write.c,42 :: 		EnableInterrupts();
EI	R30
;HID_Read_Write.c,44 :: 		HID_Enable(&readbuff,&writebuff);
LUI	R26, #hi_addr(_writebuff+0)
ORI	R26, R26, #lo_addr(_writebuff+0)
LUI	R25, #hi_addr(_readbuff+0)
ORI	R25, R25, #lo_addr(_readbuff+0)
JAL	_HID_Enable+0
NOP	
;HID_Read_Write.c,46 :: 		while(1){
L_main0:
;HID_Read_Write.c,47 :: 		while(!HID_Read())
L_main2:
JAL	_HID_Read+0
NOP	
BEQ	R2, R0, L__main11
NOP	
J	L_main3
NOP	
L__main11:
;HID_Read_Write.c,48 :: 		;
J	L_main2
NOP	
L_main3:
;HID_Read_Write.c,50 :: 		for(cnt=0;cnt<64;cnt++)
SB	R0, Offset(_cnt+0)(GP)
L_main4:
LBU	R2, Offset(_cnt+0)(GP)
SLTIU	R2, R2, 64
BNE	R2, R0, L__main12
NOP	
J	L_main5
NOP	
L__main12:
;HID_Read_Write.c,51 :: 		writebuff[cnt]=readbuff[cnt];
LBU	R3, Offset(_cnt+0)(GP)
LUI	R2, #hi_addr(_writebuff+0)
ORI	R2, R2, #lo_addr(_writebuff+0)
ADDU	R4, R2, R3
LBU	R3, Offset(_cnt+0)(GP)
LUI	R2, #hi_addr(_readbuff+0)
ORI	R2, R2, #lo_addr(_readbuff+0)
ADDU	R2, R2, R3
LBU	R2, 0(R2)
SB	R2, 0(R4)
;HID_Read_Write.c,50 :: 		for(cnt=0;cnt<64;cnt++)
LBU	R2, Offset(_cnt+0)(GP)
ADDIU	R2, R2, 1
SB	R2, Offset(_cnt+0)(GP)
;HID_Read_Write.c,51 :: 		writebuff[cnt]=readbuff[cnt];
J	L_main4
NOP	
L_main5:
;HID_Read_Write.c,53 :: 		LATB.RB0 = readbuff[63] ;
LBU	R3, Offset(_readbuff+63)(GP)
LBU	R2, Offset(LATB+0)(GP)
INS	R2, R3, 0, 1
SB	R2, Offset(LATB+0)(GP)
;HID_Read_Write.c,54 :: 		writebuff[0] = ++Count;
LH	R2, 0(SP)
ADDIU	R2, R2, 1
SH	R2, 0(SP)
SB	R2, Offset(_writebuff+0)(GP)
;HID_Read_Write.c,56 :: 		while(!HID_Write(&writebuff,64))
L_main7:
ORI	R26, R0, 64
LUI	R25, #hi_addr(_writebuff+0)
ORI	R25, R25, #lo_addr(_writebuff+0)
JAL	_HID_Write+0
NOP	
BEQ	R2, R0, L__main13
NOP	
J	L_main8
NOP	
L__main13:
;HID_Read_Write.c,57 :: 		;
J	L_main7
NOP	
L_main8:
;HID_Read_Write.c,58 :: 		}
J	L_main0
NOP	
;HID_Read_Write.c,59 :: 		}
L_end_main:
L__main_end_loop:
J	L__main_end_loop
NOP	
; end of _main
